AN201 vishay siliconix document number: 70600 05-aug -99 www.vishay.com 1 high-performance multiplexing with the dg408 the dg408 and dg409, new multiplexers from v ishay silico- nix, represent a new generation of high-performance multiplexers and demultiplexers with many specific improve- ments over existing products available today. built with the company?s high-voltage silicon-gate technology, these new ics offer significantly reduced on-resistance (<100 ), leakage currents (i s(off) < 0.5 na), power dissipation (2.25 mw), and much faster switching (250 ns) over older industry standards. these improved specifications allow designers to greatly reduce system errors and improve system performance. the dg408 and dg409 will enhance two primary multiplexer and demultiplexer applications: communications and teleme- try. important multiplexer specifications depend on the application and the accuracy required by the system. for example, in communications, switching speed is important; whereas, in telemetry, on-resistance, charge injection, and output capacitance are critical because they determine the accuracy of the system. this article will present examples of these types of applications and discuss the benefits that these new multiplexers bring to their system performance. communications the digital telephone exchange is a communication multiplexed system. in this type of system (see figure 1), a number of telephone channels carrying speech are sequentially switched (i.e., multiplexed) for fixed periods of time into an analog-to-digital converter. once converted to a digital form, the dif ferent speech signals can be processed and routed within the exchange. a typical specification for the voice bandwidth in a telephone exchange is 3.3 khz. for this bandwidth, an 8-khz sampling rate is sufficient (i.e., sampling rate > 2 times the bandwidth). therefore, each sampling period is 125 s, during which time, each of the 32 channels of the multiplexer must be addressed. this means that each channel will be turned on for 3.906 s (125 s/32). this figure is ideal, since the multiplexer cannot switch in zero time. depending on the particular multiplexer used, there will either be an overlap between sampling pulses (i.e., make-before-break switching), which leads to crosstalk between channels, or a separation between samples (i.e., break-before-make switching), which reduces the sampling time of a particular channel and results in lower multiplexer efficiency. the dg408 has switching times (250 ns) guaran- teed to be more than four times faster than previously available (1 s) multiplexers. its guaranteed break-before-make time (10 ns) prevents crosstalk during switching transitions. out in 1 in 32 figure 1. 32-channel multiplexed system address bus dg408 dg408 dg408 dg408
AN201 vishay siliconix www.vishay.com 2 document number: 70600 05-aug -99 telemetry telemetry offers many applications for multiplexer and demultiplexer combinations. a telemetry system uses transducers (a device which converts a physical variable, such as pressure, flow, temperature, etc. to an electrical equivalent) to measure variables, which are fed back via a multiplexer, monitored, and acted upon if necessary. figure 2 shows the position of a multiplexer in a high-performance, closed-loop telemetry system. the transducer output generally produces an analog output (which may need preamplification and filtering prior to multiplexing). with a wide variety of transducer types available, the inputs to the multiplexer may take many forms, including high-frequency, dc, high-level, low-level, voltage, current, and differential signals. whether a signal requires preconditioning before being multiplexed depends on the total accuracy required of the system. because the multiplexer follows the transducer output, the multiplexer specification will have a significant bearing on the system accuracy. for example, a low-level signal can, potentially, require preamplification. a primary source of error with a low-level signal may be the switching transients present in the multiplexer. these transients are the result of charge injection from the switches, producing an error voltage (usually positive for a cmos switch) which appears at the multiplexer output. hence, the lower the signal level, the greater the error introduced by the charge injection of the switch. for example, the dg408 with its 20-pc (typical) charge injection will create a 20-mv offset error when switching into a 1000-pf load. for low-level signals, this offset may be excessive. using a dif ferential multiplexer, such as the dg409, will p rovide at least an order of magnitude improvement in the total offset error. high-level signals become a potential problem at different values, depending on the technology used to manufacture the multiplexer. for a cmos multiplexer, high-level signals greater than the positive and negative supplies must be avoided to prevent permanent damage to the device. if the supplies are exceeded by the analog signal, the inherent source/drain-to-supply diodes (figure 3) will become forward biased. when the expected overloads have a short duration, usually a couple of switching diodes used in series with the supply leads will prevent permanent damage by blocking the flow of reverse current in the power supply loads. differential signals can be generated by bridge-type transducers. these devices will produce a signal of two components: a common-mode signal which is large and a small difference signal. it is the difference component that conveys the measurement information. figure 4 shows the dg409 differential multiplexer being buffered by a full differential amplifier which rejects the unwanted common-mode voltage. the amplifier output consists solely of the differential signal. the ability of the differential multiplexer to reject unwanted common-mode voltages makes it especially useful in systems where pick-up of electrical noise is a concern. a/d converter transducers multiplexer dg408 link processor demultiplexer dg408 d/a converter figure 2. position of the multiplexer in a telemetry system
AN201 vishay siliconix document number: 70600 05-aug -99 www.vishay.com 3 s d control figure 3. cmos switch showing inherent diodes ? v +v ? v +v high-frequency signals above a couple of mhz can limit system accuracy, whether its specific channel is on or off. when the device is turned on, the signal is filtered to some degree by the distributed resistance and capacitance of the signal path through the multiplexer. when the device is turned off, the high frequency couples with adjacent channels through the ? off ? channel to the output, thereby adding to the system error. what makes the dg408/409 a good multiplexer? choosing a technology for a multiplexer can depend on many factors, including the environment, its ruggedness, the accuracy required, and the cost. the choice is often a compromise between these factors. the dg408/409 is fabricated with high-voltage cmos technology developed specifically by vishay siliconix to enhance the analog switch/multiplexer range. the processing steps include a buried layer which prevents the formation of the inherent scr found in cmos structures. this immunity to latch-up makes the dg408/409 particularly insensitive to transient conditions which could occur in a remote multiplexer environment. figure 5 shows a typical profile, including the inherent parasitic components. under specific conditions (inputs exceeding the supplies), one or more of the pn junctions becomes forward biased and, under normal conditions, would result in the pnpn structure turning on. this would appear as a short circuit across the supply and would persist until the power was removed or the device burned up. using the ? buried layer ? , the gain of the pnpn structure has been reduced to less than unity. this effect makes device latch-up virtually impossible. accuracy errors introduced by a multiplexer can be split into dc and ac components. steady-state errors in a multiplexer are due to the on-resistance and finite leakage of the switch. two sources of dc error can be quantified by input offset = r s i s(off) where r s = source resistance i s = source leakage r ds(on) = on-resistance i d(on) = drain on-state leakage. ? v +v ? + lm101d difference signal out address dg409 s 1a s 4a s 1b s 4b 100 k figure 4. differential multiplexer 100 k 100 k 100 k
AN201 vishay siliconix www.vishay.com 4 document number: 70600 05-aug -99 p+ n+ n+ p+ n+ p+ p+ n+ n-channel p-channel silicon gate s d v ? v+ p-well expitaxial layer (n ? ) p+ buried layer n ? substrate silicon gate s d figure 5. cross section of a high voltage silicon gate cmos device ? + a/d converter link processor d/a converter link multiplexer dg408 thermo couple strain gauge reference voltage amplifier demultiplexer dg408 pump meter r ds(on) i d(on) i bias figure 6. typical data aquisition system figure 6 shows a typical data multiplexing system. because the multiplexer feeds a very high impedance, its input offset is a function of its on-resistance and the on-state leakage of the switch plus the amplifier bias current. v offset = r ds(on) (i d(on) + i (bias) ) for the dg408/409 typical specifications, this offset will be v offset = 100 (500 pa + 30 pa) = 53 nv
AN201 vishay siliconix document number: 70600 05-aug -99 www.vishay.com 5 this typical offset (at 25 c) should be compared with the signal level to determine whether the error introduced by the offset is acceptable. another source of error that may be introduced by the switch occurs when the switch changes state. transients (due to capacitive coupling between the drivers and drain) can be manifested as an error voltage appearing on the output node. the effect of charge injection is measured in volts and is given by v = q i /c where q i is the injected charge in picocoulombs c is the load capacitance at the output. the dg408/409 devices have been internally compensated to minimize the effects of the injection. this is achieved by including compensation capacitors on the output switch. these capacitors are sized to produce an equal and opposite transient which tends to cancel out the effect of the switch injection. typical charge injection for the dg408/409 is 20 pc for the test configuration shown in figure 7. 10 nf dg408 address sw off switch on sw off v source = 0 v r source = 0 r source v source v o v o v o figure 7. charge injection test circuit switching speed multiplexers operate in real time (i.e., samples are taken sequentially and represent the analog input signal). obviously, the quicker a multiplexer changes state, the more samples can be taken in a given time. fast switching operation is often difficult to achieve using larger multiplexing devices. that is, the greater the number of channels, the slower the speed due to additional capacitance at the common output node. the dg408/409 switching speed (t trans ) is 250 ns maximum at room temperature with a 10-ns minimum break-before- make time. while this break-before-make time prevents overlap or ? alias ? between channels, it reduces multiplexer efficiency and, therefore, is kept as short as possible. a channel-switching rate (figure 8) is defined for the dg408/409 by t on , t off , and t sample , where t sample is dependent on the application. channel 1 channel 2 t off t on t sample figure 8. channel switching rate assuming a t sample of 1.2 s, the maximum switching rate for the dg408/409 (with no pulse-edge overlap) is once every 1.5 s or a frequency of 666 khz. this example shows that the switching speed of the dg408/409 is not a significant factor unless the t sample time becomes much smaller. for multi-channel systems, if the sampling theorem is obeyed, the maximum switching rate will limit the number of channels and/or the maximum frequency components of any of the channel inputs. techniques are available to improve the switching rate, and an example using the dg408/409 and dg400 will be shown later. versatility with cmos switches, signal conduction is the same in either direction. the refore, as shown in figure 9, it ? s possible to use the dg408 as a demultiplexer with one input from the digital-to-analog converter and 8 outputs. dg408 d/a converter digital output from processor out 1 out 8 figure 9. using the dg408 as a demultiplexer
AN201 vishay siliconix www.vishay.com 6 document number: 70600 05-aug -99 this versatility allows the same advantages at the ? back end ? of the system ? that is, a single wire can be used to carry all the control signals to the remote site. then the control signals may be converted back to analog form and demultiplexed for controlling the system. logic compatibility the compatibility of the multiplexer is a measure of how easy it is to interface with other system components, such as transducers, a/d converters, power supplies, the environment, etc. the dg408/409 has many features which make this interfacing as easy as possible. for example, a regulator has been included on the chip to provide stability against power supply and temperature variations. the regulator maintains ttl compatibility over power supply variations, while the dynamic specifications can be met over the full military temperature range. the regulation also guarantees a low current consumption of 75 a, making it suitable for battery/portable applications. application enhancements the following examples of applications using the dg408/409 are intended to highlight some specific improvements over their predecessors. sample-and-hold circuits using analog multiplexers are widely used in analog signal processing and data conversion systems to store analog voltages accurately over time periods ranging from nanoseconds to several minutes. this ab ility finds many applications, including data distribution systems, simultaneous sample-and-hold designs, sampling oscilloscopes, digital volt meters, signal reconstruction filters, and analog computational circuits. alt hough they are theoretically simple, these high-speed, high-accuracy circuits need careful consideration in their design. figure 10 shows the dg408 in a sample-and-hold circuit. during the sample phase, one switch in the analog multiplexer is closed and the hold capacitor is charged to the input voltage via the on-state switch. once the capacitor is charged to its final value, the hold mode is entered by opening the switch. during the hold mode, the capacitor voltage can be examined via the low-leakage buffer. by repeating this with other switches in the multiplexer, many analog inputs can be sequentially examined. in a high-speed system, an important specification for the circuit designer is the acquisition time of the sample-and-hold system ? that is, the time delay between the sample command and the capacitor reaching its final value. figure no tag shows that the acquisition time is dependent on two factors. the first factor is the time from when the sample command is given to when the switch is turned on (i.e., the t on of the switch). for the dg408, the t on is guaranteed as 250 ns maximum at 25 c; this translates to a 4 times improvement over existing pin-compatible devices. the second contribution to acquisition time is the time taken for the hold capacitor to charge to its final value. the charging time is determined by the source impedance of the analog source, the on-resistance of the switch, and the hold capacitor. hence, for low-impedance analog sources, the on-resistance of the switch will play an important part in determining the time constant. the on-resistance of the dg408/409 is guaranteed at 100 over the whole analog voltage range, making a 500% improvement over existing pin-compatible parts. ? + ? + a/d converter dg408 amplifier low leakage buffer to processor in 1 in 2 c h figure 10. high performance sample/hold circuit
AN201 vishay siliconix document number: 70600 05-aug -99 www.vishay.com 7 (capacitor voltage) sample command switch delay capacitor charging error band time acquisition v c (t on ) time (t a ) figure 11. acquisition time of a sample/hold system to illustrate the improvements in acquisition time made possible with the dg408/409, consider the following comparison with the dg508a pin-compatible multiplexer. the acquisition time is t a = t on + n (r s + r ds(on) ) x c h where n is the number of time constants (determined by the accuracy required). r s is the source resistance of the analog input while c h is the hold capacitor. if c h = 100 pf r s = 50 n = 10 then for the dg508a, t a = 1.5 s + 10 (50 + 450) 100 pf t a = 1.5 s + 500 ns t a = 2 s. using the same conditions for the dg408, t a = 250 ns + 10 (50 +100) x 100 pf t a = 250 ns + 150 ns t a = 400 ns. thus, by using the dg408, the acquisition time is improved by 5 times. for high-accuracy systems, an important consideration is the sample-to-hold offset error. this error arises when the switch turns off and charge is injected by the switch onto the hold capacitor, adding an error to the stored analog voltage. the error is related to the hold capacitor by v o = q i /c h where v o is the offset error q i is the injected charge c h is the hold capacitor. as an example of the possible improvement with the dg408, a comparison is drawn with the dg508a. assuming a 1-nf hold capacitor, for the dg508a, v o = 50 pc 1 nf = 50 mv and for the dg408, v o = 20 pc 1 nf = 20 mv. thus, a 2.5-fold improvement in error voltage is provided by using the dg408. the ability of the system to store the analog sample when the switch goes off is referred to as the droop rate. it is measured as the change in voltage versus time while in the hold mode. the droop rate depends on bias current of the amplifier, the leakage of the capacitor, and the off-state leakage of the multiplexer. the low-leakage performance of the dg408/409 allows a lower droop rate (i.e., a more accurate storage of the analog sample).
AN201 vishay siliconix www.vishay.com 8 document number: 70600 05-aug -99 high-speed switching in large segments of the electronics industry, speed is a primary concern in product design. computer graphics, video equipment, and medical electronics are a few examples where high-speed switching is required. the activation frequency of a multiplexer (i.e., the frequency at which the switch can be toggled) is directly related to the switching speed of the device (i.e., the faster the switching speed, the higher the activation frequency). the dg408 has guaranteed maximum of 250 ns switching speed, thus making it theoretically possible to toggle the switch up to 2 mhz. figure 12 shows how a two-level multiplexer can be used to increase the data transmission rates in an analog multiplexed system. use of the two-level system gives improved performance over a single-level system. examples of these improvements are listed below. output capacitance results only from the second-level device and not from the sum of the first-level devices. the leakage currents at the output node will be reduced from the sum of the second-level devices to that of the second-level device. in a design where one multiplexer is sampled while the other is switched, the switching speed of the system is increased to that of the dg400. crosstalk and isolation are improved because one-half of the system will have two off switches in series to the output node at any given time. differential multiplexing of low-level signals when multiplexing low-level signals, careful choice of a multiplexer and handling of the system layout helps avoid signal masking by ac noise pick-up and dc voltages generated by thermocouple effects. to transmit the signal effectively, several factors must be considered. single-ended or differential signal paths low-level transmission or preamplification the type of conductor the choice between a single-ended (dg408) or differential (dg409) multiplexer is really a function of the system. cost will dictate a single-ended connection, and for a high signal level, the shorter distance should provide a stable-environment system. for a system that has a significant signal path length and is potentially being routed in a noisy environment (e.g., motors), common-mode signals can be picked up. for low-level signal transmission, this common-mode signal will provide a significant error. to minimize the effect of the common-mode signals, a twisted pair of wires feed a differential multiplexer, such as the dg409, which is buffered by a differential amplifier that rejects the unwanted common-mode portion of the signal (see figure 13). dg408 ? v +v dg411 +v ? v in 1 in 32 figure 12. two-level multiplexing with the dg408
AN201 vishay siliconix document number: 70600 05-aug -99 www.vishay.com 9 instrumentation amplifier ? + a/d dg409 ? 15 v +15 v output converter tc 1 tc 2 tc 3 tc 4 a v = 100 a 0 a 1 figure 13. differential multiplexing of thermocouples the advantages of low-level or high-level transmission is again dictated by system configuration and cost. preamplification at the transducer will provide low source impedance and voltage gain, but it introduces the problem of supplying power to the amplifier. the transmission cable carrying the transducer signal is critical in a low-level system; it should be as short as practical. signal conductors should be tightly twisted for minimum enclosed area. this technique guards against picking up electromagnetic interference and shields the twisted pair of wires against capacitively-coupled (electrostatic) interference. a key requirement for the transmission cable is that it presents a balanced line to the source of noise interference. this requires an equal series impedance in each conductor and an equally distributed impedance from each conductor to ground. the result should be that noise will be coupled in phase to both conductors and rejected as common-mode voltages. coaxial cable is not suitable for low-level signals because the two conductors (center and shield) are unbalanced. also ground loops are produced if the shield is grounded at both ends by standard baby ? n ? connector sockets. if coaxial cable is used, the signal should be carried on the center conductors of two equal-length cables whose shield is terminated only at the transducer end. silicon in contact with aluminum creates a thermocouple voltage. in a typical multiplexer, the source voltage will be exactly canceled by the drain voltage, but large thermal gradients between source and drain contacts can produce a net offset voltage. the low current consumption of the dg409 ( 75 a) translates into minimal errors due to thermocouple offsets. programmable amplifier figure 14 shows a programmable amplifier with selectable inputs. this configuration is used in auto-ranging digital volt meters, signal conditioners, etc. its purpose is to select optimum gain ready for conversion. gain ratios are a function of the resistor ratios. sources of error will be due to the on-resistance of the switches contributing to the resistor ratio. the low on-resistance of the dg408 (typically 40 at 25 c) and close matching should minimize ranging errors introduced by the switches. the switching speed of the dg408 will allow the preferred value of gain to be attained quickly.
AN201 vishay siliconix www.vishay.com 10 document number: 70600 05-aug -99 dg408 ? + ? 15 v +15 v dg408 selectable inputs amplifier lm101a gain set by resistor ratios gain selected by address sw 1 selected ? gain = 1 sw 2 selected ? gain = 10 sw 3 selected ? gain = 100 sw 8 selected ? gain = 1000 a 0 a 1 a 2 in 1 in 8 sw 1 sw 8 18 k 2 k 9.9 k 100 100 k 100 figure 14. programmable amplifier with selectable inputs conclusion for multiplexers to maintain their usefulness in high-performance systems, their design must incorporate the latest technological advances. as digital controllers are becoming faster and analog sources more accurate, the modern multiplexer must reflect these advances to become a stronger link in the transition from the analog to the digital world. the dg408 and dg409 are designed to meet these new requirements in the marketplace and reflect vishay siliconix ? commitment to serve our customers ? needs for state-of-the-art technology. references analog switches and their applications , vishay siliconix, june 1980. bylanski, p., digital t ransmission systems , peter peregrinus, ltd., 1976.
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